Our research interests are focused on the analysis of the worst-case execution/response time (WCET/WCRT) of critical real-time software.

Wondering what WCET analysis is? See here (English) or here (French – much more detailed)

We mainly use static analysis techniques, such as abstract interpretation (instead of measurements).

Current topics

• Flow analysis: to determine an upper bound on the execution time, one must at least determine loop bounds. Identifying infeasible path helps to increase precision. 
• Microarchitecture-level timing analysis:
  • we use the IPET method to upper bound the worst-case execution time of a piece of code: it determine the longest path in the control flow graph by combining the individual execution costs of basic blocks. We work on approaches to derive these costs considering modern pipelined processors. Our latest contribution is based on XDDs (eXecution Decision Diagrams). Read more …
  • the behavior of instruction and data caches needs to be accurately analyzed to determine the latencies of accesses to the memory. We contribute to this topic too.
• Interference analysis: on a multicore platform, conflicts that may arise when multiple cores need to access the shared memory are likely generate delays and to increase latencies. Accounting for such delays is required to estimate worst-case execution and response times. Our approach is based on Timing Interest Points (TIPs).   Read more …
• Timing analysis of GPU-accelerated software: we have recently started to work on the timing analysis of Cuda code.
• Design of timing-predictable processors: we also investigate how to make a CPU core timing-predictable, so that it is possible to derive sound and accurate WCET estimations for a piece of code.