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VeriSync project
VeriSync: Scientific production
Publications and formal developments
M. Strecker:
Clock type soundness in synchronous languages
(Project Deliverable 2 (report and formalization))
N. Baklanova, M. Strecker:
Abstraction and Verification of Properties of a Real-Time Java
(Project Deliverable 4 (report))
V.C. Ngo, J-P. Talpin, T. Gautier, P. Le Guernic, L. Besnard:
Formal Verification of Synchronous Data-flow Program Transformations - Toward Certified Compilers
(part of Project Deliverable 5)
V.C. Ngo, J-P. Talpin, T. Gautier, P. Le Guernic, L. Besnard:
Formal verification of compiler transformations on polychronous equations
(part of Project Deliverable 5, see the
Gforge
for the implementation)
V.C. Ngo, J-P. Talpin, T. Gautier, P. Le Guernic, L. Besnard:
Formal Verification of Automatically Generated C-code from Polychronous Data-flow Equations
N. Baklanova, M. Strecker:
A Formal Model of Resource Sharing Conflicts in Multi-Threaded Java
(part of Project Deliverable 6 (report))
S. Djeddai, M. Strecker, M. Mezghiche:
Integrating a Formal Development for DSLs into Meta-modeling
(part of Project Deliverable 7)
S. Djeddai, M. Mezghiche, M. Strecker:
A Case Study in Combining Formal Verification and Model-Driven Engineering
(part of Project Deliverable 7)
Code
SigCert - Signal Compiler Certification
Last modified: Sat Jul 20 12:03:08 CEST 2013