BHWiki.ResearchInterestsAndProjects History

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June 08, 2020, at 12:51 PM by 141.115.28.6 -
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'''[+Under review projects+]'''
----
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[['''[+Ongoing projects+]'''
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'''[+Ongoing projects+]'''
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#'''SecSafi (2019-2022):'''Security and Safety Interplay''.-- IRIT-CEA research project''
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'''1. SecSafi (2019-2022):'''Security and Safety Interplay''.-- IRIT-CEA research project''
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#'''CybserSec4Europe (2018-2022):''' ''CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using''
to:
'''2. CybserSec4Europe (2018-2022):''' ''CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using''
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#'''ISARP (2017-2020):''' ''Interplay of Security and Software ARchitecture Patterns: Formal Foundations, Development framework and Evaluation.-- CIMI research project''
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'''3. ISARP (2017-2020):''' ''Interplay of Security and Software ARchitecture Patterns: Formal Foundations, Development framework and Evaluation.-- CIMI research project''
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#'''CBSE-PBSE (2014-2017):'''Component-Based Software engineering and Pattern-Based Security Engineering''.-- IRIT-CEA research project''
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'''1. CBSE-PBSE (2014-2017):'''Component-Based Software engineering and Pattern-Based Security Engineering''.-- IRIT-CEA research project''
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#'''TERESA (2009-2013):''' ''Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
to:
'''2. TERESA (2009-2013):''' ''Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
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#'''SIRSEC(2009-2013):''' ''Systeme d'Information Reparti Securitaire -- FUI7''
to:
'''3. SIRSEC(2009-2013):''' ''Systeme d'Information Reparti Securitaire -- FUI7''
June 08, 2020, at 12:49 PM by 141.115.28.6 -
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*'''[+Ongoing projects+]'''
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[['''[+Ongoing projects+]'''
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June 08, 2020, at 12:48 PM by 141.115.28.6 -
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'''[+Ongoing projects+]'''
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*'''[+Ongoing projects+]'''
June 08, 2020, at 12:48 PM by 141.115.28.6 -
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'''1. SecSafi (2019-2022):'''Security and Safety Interplay''.-- IRIT-CEA research project''
to:
#'''SecSafi (2019-2022):'''Security and Safety Interplay''.-- IRIT-CEA research project''
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'''2. CybserSec4Europe (2018-2022):''' ''CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using''
to:
#'''CybserSec4Europe (2018-2022):''' ''CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using''
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'''3. ISARP (2017-2020):''' ''Interplay of Security and Software ARchitecture Patterns: Formal Foundations, Development framework and Evaluation.-- CIMI research project''
to:
#'''ISARP (2017-2020):''' ''Interplay of Security and Software ARchitecture Patterns: Formal Foundations, Development framework and Evaluation.-- CIMI research project''
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'''1. CBSE-PBSE (2014-2017):'''Component-Based Software engineering and Pattern-Based Security Engineering''.-- IRIT-CEA research project''
to:
#'''CBSE-PBSE (2014-2017):'''Component-Based Software engineering and Pattern-Based Security Engineering''.-- IRIT-CEA research project''
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'''2. TERESA (2009-2013):''' ''Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
to:
#'''TERESA (2009-2013):''' ''Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
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'''3. SIRSEC(2009-2013):''' ''Systeme d'Information Reparti Securitaire -- FUI7''
to:
#'''SIRSEC(2009-2013):''' ''Systeme d'Information Reparti Securitaire -- FUI7''
June 08, 2020, at 12:39 PM by 141.115.28.6 -
June 08, 2020, at 12:37 PM by 141.115.28.6 -
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'''1. CBSE-PBSE (2014-2017):''' ''.-- IRIT-CEA research project''
The goal of the CBSE-PBSE project is
to:
'''1. CBSE-PBSE (2014-2017):'''Component-Based Software engineering and Pattern-Based Security Engineering''.-- IRIT-CEA research project''
The
goal of the CBSE-PBSE project is to develop an integrated design framework for the specification and analysis of secure
software architectures, using models, patterns and risk analysis.
June 08, 2020, at 12:33 PM by 141.115.28.6 -
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'''1. SecSafi (2019-2022):''' ''.-- IRIT-CEA research project''
to:
'''1. SecSafi (2019-2022):'''Security and Safety Interplay''.-- IRIT-CEA research project''
June 08, 2020, at 12:32 PM by 141.115.28.6 -
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The goal of the SecSafi project is
to:
In the context of SecSafi project, we will focus particularly on the interplay between safety, security and the system architecture; we
aim at providing methodological and tool support for their design in unison using modeling, formal techniques and patterns.
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'''SecSafi (2019-2022):''' ''.-- IRIT-CEA research project''
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'''1. SecSafi (2019-2022):''' ''.-- IRIT-CEA research project''
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'''CybserSec4Europe (2018-2022):''' ''CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using''
to:
'''2. CybserSec4Europe (2018-2022):''' ''CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using''
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'''ISARP (2017-2020):''' ''Interplay of Security and Software ARchitecture Patterns: Formal Foundations, Development framework and Evaluation.-- CIMI research project''
to:
'''3. ISARP (2017-2020):''' ''Interplay of Security and Software ARchitecture Patterns: Formal Foundations, Development framework and Evaluation.-- CIMI research project''
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'''CBSE-PBSE (2014-2017):''' ''.-- IRIT-CEA research project''
to:
'''1. CBSE-PBSE (2014-2017):''' ''.-- IRIT-CEA research project''
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'''TERESA (2009-2013):''' ''Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
to:
'''2. TERESA (2009-2013):''' ''Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
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'''SIRSEC(2009-2013):''' ''Systeme d'Information Reparti Securitaire -- FUI7''
to:
'''3. SIRSEC(2009-2013):''' ''Systeme d'Information Reparti Securitaire -- FUI7''
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'''[+On going projects+]'''
to:
'''[+Ongoing projects+]'''
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'''[+Under review projects+]'''
----
June 08, 2020, at 12:19 PM by 141.115.28.6 -
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'''[+On going project+]'''
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'''[+On going projects+]'''
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'''CBSE-PBSE (2014-2027):''' ''.-- IRIT-CEA research project''
to:

'''[+Completed projects+]'''
----

'''CBSE-PBSE (2014-2017
):''' ''.-- IRIT-CEA research project''
June 08, 2020, at 12:19 PM by 141.115.28.6 -
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[+On going project+]
to:
'''[+On going project+]'''
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----
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[+On going project+]
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'''SecSafi (2019-2022):''' ''.-- IRIT-CEA research project''
The goal of the SecSafi project is
\\
Partners are:
* IRIT Toulouse (France) : Software architecture, Formal modeling, security patterns
* CEA (France): Modeling, Safety patterns
June 08, 2020, at 12:13 PM by 141.115.28.6 -
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'''CBSE-PBSE (2014-2027):''' ''.-- IRIT-CEA research project''
The goal of the CBSE-PBSE project is
\\
Partners are:
* IRIT Toulouse (France) : Software architecture, security patterns
* CEA (France): Modeling
June 08, 2020, at 12:12 PM by 141.115.28.6 -
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June 08, 2020, at 12:07 PM by 141.115.28.6 -
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The goal of the ISARP project is to improve this research by investigating more concepts, more semantics to define a new formal modeling paradigm for compositional security within a pattern-based approach as a foundation for novel system security engineering practices. ISARP aims at proposing a development framework for handling the composition and integration of security and architecture solutions that semi-automatically supports their validation.
June 08, 2020, at 12:06 PM by 141.115.28.6 -
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* IRIT Toulouse (France) : Modeling, security patterns
to:
* IRIT Toulouse (France) : Modeling, software architecture, security patterns
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* FAU (USA): Security patterns
to:
* FAU (USA): Security patterns
* Monash (Australie): Formal modeling
June 08, 2020, at 12:02 PM by 141.115.28.6 -
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* Fraunhoder (Germany): Formal modeling
to:
* Fraunhoder (Germany): Formal modeling
* FAU (USA): Security patterns
June 08, 2020, at 11:47 AM by 141.115.28.6 -
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'''TERESA (2009-2013):''' ''Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
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'''TERESA (2009-2013):''' ''Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
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'''SIRSEC(2009-2013):''' ''Systeme d'Information Reparti Securitaire -- FUI7''
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'''SIRSEC(2009-2013):''' ''Systeme d'Information Reparti Securitaire -- FUI7''
June 08, 2020, at 11:46 AM by 141.115.28.6 -
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%lframe width=150px height=55px% [[ https://cybersec4europe.eu/ | Attach:png_csfe_logo.png]]
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%lframe width=150px height=55px% [[ https://cybersec4europe.eu/ | Attach:png_csfe_logo.png]]
June 08, 2020, at 11:46 AM by 141.115.28.6 -
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''ISARP (2017-2020): Interplay of Security and Software ARchitecture Patterns: Formal Foundations, Development framework and Evaluation.-- CIMI research project''
to:
'''ISARP (2017-2020):''' ''Interplay of Security and Software ARchitecture Patterns: Formal Foundations, Development framework and Evaluation.-- CIMI research project''
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''TERESA (2009-2013):Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
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'''TERESA (2009-2013):''' ''Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
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''SIRSEC(2009-2013): Systeme d'Information Reparti Securitaire -- FUI7''
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'''SIRSEC(2009-2013):''' ''Systeme d'Information Reparti Securitaire -- FUI7''
June 08, 2020, at 11:45 AM by 141.115.28.6 -
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''CybserSec4Europe (2018-2022): CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using''
to:
'''CybserSec4Europe (2018-2022):''' ''CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using''
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''ISARP (2017-2020): Interplay of Security and Software ARchitecture Patterns: Formal Foundations, Development framework and Evaluation.-- CIMI research project''
\\\\
Partners are:
* IRIT Toulouse (France) : Modeling, security patterns
* Fraunhoder (Germany): Formal modeling
June 08, 2020, at 11:42 AM by 141.115.28.6 -
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''CybserSec4Europe: CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using''
to:
''CybserSec4Europe (2018-2022): CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using''
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''TERESA:Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
to:
''TERESA (2009-2013):Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
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''SIRSEC: Systeme d'Information Reparti Securitaire(2009-2013) -- FUI7''
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''SIRSEC(2009-2013): Systeme d'Information Reparti Securitaire -- FUI7''
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best practice examples derived from concepts like CERN as well the expertise and experience of partners. -- H2020 '' https://cybersec4europe.eu/
to:
''best practice examples derived from concepts like CERN as well the expertise and experience of partners. -- H2020 '' https://cybersec4europe.eu/
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'' CybserSec4Europe: CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using
to:
''CybserSec4Europe: CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using''
June 08, 2020, at 11:40 AM by 141.115.28.6 -
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''CybserSec4Europe: CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using
best practice examples derived from concepts like CERN as well the expertise and experience of partners. -- H2020'' https://cybersec4europe.eu/
to:
'' CybserSec4Europe: CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using
best practice examples derived from concepts like CERN as well the expertise and experience of partners. -- H2020 '' https://cybersec4europe.eu/
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''italics''
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''italics''
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CyberSec4Europe's main objective is to pilot the consolidation and future projection of the cybersecurity capabilities required to secure and maintain European democracy and the integrity of the Digital Single Market. CyberSec4Europe has translated this broad objective into measurable, concrete steps: three policy objectives, three technical objectives and two innovation objectives.

With over 100 cybersecurity projects between them, the CyberSec4Europe consortium members cover a wide spectrum of cybersecurity issues: 14 key cybersecurity domain areas, 11 technology/applications elements and nine crucial vertical sectors.
to:
CyberSec4Europe's main objective is to pilot the consolidation and future projection of the cybersecurity capabilities required to secure and maintain European democracy and the integrity of the Digital Single Market. CyberSec4Europe has translated this broad objective into measurable, concrete steps: three policy objectives, three technical objectives and two innovation objectives. With over 100 cybersecurity projects between them, the CyberSec4Europe consortium members cover a wide spectrum of cybersecurity issues: 14 key cybersecurity domain areas, 11 technology/applications elements and nine crucial vertical sectors.
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\\\\
Partners are:
With over 100 cybersecurity projects between them, the CyberSec4Europe consortium members cover a wide spectrum of cybersecurity issues: 14 key cybersecurity domain areas, 11 technology/applications elements and nine crucial vertical sectors.
to:
With over 100 cybersecurity projects between them, the CyberSec4Europe consortium members cover a wide spectrum of cybersecurity issues: 14 key cybersecurity domain areas, 11 technology/applications elements and nine crucial vertical sectors.
June 08, 2020, at 11:37 AM by 141.115.28.6 -
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June 08, 2020, at 11:37 AM by 141.115.28.6 -
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Partners are:
* IRIT Toulouse (France) : modelling, dependability
*
Fraunhofer (Germany): Formal validation of security and dependability
*
Trialog (France): tools, trust models elicitation, home control, automotive applications
* Ikerlan-K4 (Spain): industry control applications
*
Escrypt (Germany): security for embedded systems
* U
.Siegen (Germany): security for metrology
to:
Partners are: With over 100 cybersecurity projects between them, the CyberSec4Europe consortium members cover a wide spectrum of cybersecurity issues: 14 key cybersecurity domain areas, 11 technology/applications elements and nine crucial vertical sectors.
June 08, 2020, at 11:36 AM by 141.115.28.6 -
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''CybserSec4Europe: -- H2020'' https://cybersec4europe.eu/



%lframe
width=150px height=55px% [[ http://www.teresa-project.org/ | Attach:logoTERESA.jpg]]
''TERESA:Trusted
computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
The
work is conducted in the context of Small or medium-scale focused research project (STREP) proposal ICT Call 4 FP7-ICT-2009-4.
The
objective of TERESA is to define, demonstrate and validate an engineering discipline for trust that is adapted to resource constrained embedded systems. We define trust as the degree with which security and dependability requirements are met.
to:
''CybserSec4Europe: CyberSec4Europe is designing, testing and demonstrating potential governance structures for a future European Cybersecurity Competence Network using
best
practice examples derived from concepts like CERN as well the expertise and experience of partners. -- H2020'' https://cybersec4europe.eu/



CyberSec4Europe's
main objective is to pilot the consolidation and future projection of the cybersecurity capabilities required to secure and maintain European democracy and the integrity of the Digital Single Market. CyberSec4Europe has translated this broad objective into measurable, concrete steps: three policy objectives, three technical objectives and two innovation objectives.


\\\\
Partners are:
* IRIT Toulouse (France) : modelling, dependability
* Fraunhofer (Germany): Formal validation of security and dependability
* Trialog (France): tools, trust models elicitation, home control, automotive applications
* Ikerlan-K4 (Spain): industry control applications
* Escrypt (Germany): security for embedded systems
* U.Siegen (Germany): security for metrology
June 08, 2020, at 11:32 AM by 141.115.28.6 -
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%lframe width=150px height=55px% [[ https://cybersec4europe.eu/ | Attach:CSfE_Logo_Reverse.png]]
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%lframe width=150px height=55px% [[ https://cybersec4europe.eu/ | Attach:png_csfe_logo.png]]
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%lframe width=150px height=55px% [[ https://cybersec4europe.eu/ | Attach:CSfE_Logo_Reverse.jpg]]
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%lframe width=150px height=55px% [[ https://cybersec4europe.eu/ | Attach:CSfE_Logo_Reverse.png]]
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%lframe width=150px height=55px% [[ https://cybersec4europe.eu/ | Attach:logoCS4Europe.jpg]]
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%lframe width=150px height=55px% [[ https://cybersec4europe.eu/ | Attach:CSfE_Logo_Reverse.jpg]]
June 08, 2020, at 11:28 AM by 141.115.28.6 -
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%lframe width=150px height=55px% [[ https://cybersec4europe.eu/ | Attach:logoCS4Europe.jpg]]
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"CybserSec4Europe: -- H2020" https://cybersec4europe.eu/
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''CybserSec4Europe: -- H2020'' https://cybersec4europe.eu/
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"CybserSec4Europe: -- H2020" https://cybersec4europe.eu/
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%lframe width=150px height=55px%25 Attach:logoSIRSEC.jpg
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%lframe width=150px height=55px% Attach:logoSIRSEC.jpg
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The work is conducted in the context of a national French project. Partners are:
to:
The work is conducted in the context of a national French project.
\\\\\\\

Partners are:
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%lframe width=150px height=55px%25 [[ http://www.teresa-project.org/ | Attach:logoTERESA.jpg]]
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%lframe width=150px height=55px% [[ http://www.teresa-project.org/ | Attach:logoTERESA.jpg]]
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The work is conducted in the context of Small or medium-scale focused research project (STREP) proposal ICT Call 4 FP7-ICT-2009-4
The objective of TERESA is to define, demonstrate and validate an engineering discipline for trust that is adapted to resource constrained embedded systems. We define trust as the degree with which security and dependability requirements are met. Partners are:
to:
The work is conducted in the context of Small or medium-scale focused research project (STREP) proposal ICT Call 4 FP7-ICT-2009-4.
The objective of TERESA is to define, demonstrate and validate an engineering discipline for trust that is adapted to resource constrained embedded systems. We define trust as the degree with which security and dependability requirements are met.

Partners are:
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%lframe width=150px height=55px%25 Attach:logoSIRSEC.jpg ''SIRSEC: Systeme d'Information Reparti Securitaire(2009-2013) -- FUI7''
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%lframe width=150px height=55px%25 Attach:logoSIRSEC.jpg
''SIRSEC: Systeme d'Information Reparti Securitaire(2009-2013) -- FUI7''
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The work is conducted in the context of Small or medium-scale focused research project (STREP) proposal ICT Call 4 FP7-ICT-2009-4%0a%0a%0aThe objective of TERESA is to define, demonstrate and validate an engineering discipline for trust that is adapted to resource constrained embedded systems. We define trust as the degree with which security and dependability requirements are met. Partners are:
to:
The work is conducted in the context of Small or medium-scale focused research project (STREP) proposal ICT Call 4 FP7-ICT-2009-4
The objective of TERESA is to define, demonstrate and validate an engineering discipline for trust that is adapted to resource constrained embedded systems. We define trust as the degree with which security and dependability requirements are met. Partners are:
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'''Research Interests & Projects'''
to:
!!!!%gray%'''Research Interests & Projects'''
----
\\
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'''Research Interests & Projects'''



%lframe width=150px height=55px%25 [[ http://www.teresa-project.org/ | Attach:logoTERESA.jpg]]
''TERESA:Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7'' http://www.teresa-project.org/
The work is conducted in the context of Small or medium-scale focused research project (STREP) proposal ICT Call 4 FP7-ICT-2009-4%0a%0a%0aThe objective of TERESA is to define, demonstrate and validate an engineering discipline for trust that is adapted to resource constrained embedded systems. We define trust as the degree with which security and dependability requirements are met. Partners are:
* IRIT Toulouse (France) : modelling, dependability
* Fraunhofer (Germany): Formal validation of security and dependability
* Trialog (France): tools, trust models elicitation, home control, automotive applications
* Ikerlan-K4 (Spain): industry control applications
* Escrypt (Germany): security for embedded systems
* U.Siegen (Germany): security for metrology

%lframe width=150px height=55px%25 Attach:logoSIRSEC.jpg ''SIRSEC: Systeme d'Information Reparti Securitaire(2009-2013) -- FUI7''
The work is conducted in the context of a national French project. Partners are:
*IRIT, CEA LIST and INRETS LEOST (Academics): to help the improvement of the development of distributed secure systems using model based engineering
* ALSTOM TRANSPORT and Thales (Industrials): to reduce the cost of the life cycle of development process of novel architecture with support of extended services
* PRISMTECH, SERMA Ing. and GEENSYS (Software editors): to extend their offers of middleware and tools with support of safety and validation
March 19, 2018, at 09:06 PM by 141.115.28.6 -
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'''Research Interests & Projects'''%0a----%0a\\%0a%0a%25lframe width=150px height=55px%25 [[ http://www.teresa-project.org/ | Attach:logoTERESA.jpg]]%25%25%0a!!!!!%25center%25''TERESA:Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7''%0a%25left%25 http://www.teresa-project.org/%0a%0a%0aThe work is conducted in the context of Small or medium-scale focused research project (STREP) proposal ICT Call 4 FP7-ICT-2009-4%0a%0a%0aThe objective of TERESA is to define, demonstrate and validate an engineering discipline for trust that is adapted to resource constrained embedded systems. We define trust as the degree with which security and dependability requirements are met.%0a%0aPartners are:%0a* IRIT Toulouse (France) : modelling, dependability%0a* Fraunhofer (Germany): Formal validation of security and dependability%0a* Trialog (France): tools, trust models elicitation, home control, automotive applications%0a* Ikerlan-K4 (Spain): industry control applications%0a* Escrypt (Germany): security for embedded systems%0a* U.Siegen (Germany): security for metrology%0a%0a%0a%0a----%0a%25lframe width=150px height=55px%25 Attach:logoSIRSEC.jpg%0a!!!!!%25center%25''SIRSEC: SystÚme d'Information Reparti Sécuritaire(2009-2013) -- FUI7''%0a%0a\\%0aThe work is conducted in the context of a national French project. %0a%0aPartners are:%0a%0a*IRIT, CEA LIST and INRETS LEOST (Academics): to help the improvement of the development of distributed secure systems using model based engineering %0a* ALSTOM TRANSPORT and Thales (Industrials): to reduce the cost of the life cycle of development process of novel architecture with support of extended services%0a* PRISMTECH, SERMA Ing. and GEENSYS (Software editors): to extend their offers of middleware and tools with support of safety and validation %0a----%0a!!!!!%25center%25''Inflexion Research Project Under Usine Logicielle Project(Research fellow at the CEA/Sacaly)''%0a%0a%25center%25http://www.usine-logicielle.org%0a\\%0a%0a%0aThe work is conducted in the context of a national French project called Usine Logicielle. This project is three-folded : modeling, validation and infrastructure/middleware support along with configuration support.
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(:title Research Interests & Projects:)

!!!!%gray%
'''Research Interests & Projects'''
----
\\

%lframe width=150px height=55px% [[ http://www.teresa-project.org/ | Attach:logoTERESA.jpg]]%%
!!!!!%center%''TERESA:Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7''
%left% http://www.teresa-project.org/


The
work is conducted in the context of Small or medium-scale focused research project (STREP) proposal ICT Call 4 FP7-ICT-2009-4


The
objective of TERESA is to define, demonstrate and validate an engineering discipline for trust that is adapted to resource constrained embedded systems. We define trust as the degree with which security and dependability requirements are met.

Partners
are:
* IRIT Toulouse (France) : modelling, dependability
* Fraunhofer (Germany): Formal validation of security and dependability
* Trialog (France): tools, trust models elicitation, home control, automotive applications
* Ikerlan-K4 (Spain): industry control applications
* Escrypt (Germany): security for embedded systems
* U.Siegen (Germany): security for metrology



----
%lframe width=150px height=55px% Attach:logoSIRSEC.jpg
!!!!!%center%''SIRSEC: d'Information Reparti (2009-2013) -- FUI7''

\\
The work is conducted in the context of a national French project.

Partners
are:

*IRIT, CEA LIST and INRETS LEOST (Academics): to help the improvement of the development of distributed secure systems using model based engineering
* ALSTOM TRANSPORT and Thales (Industrials): to reduce the cost of the life cycle of development process of novel architecture with support of extended services
* PRISMTECH, SERMA Ing. and GEENSYS (Software editors): to extend their offers of middleware and tools with support of safety and validation
----
!!!!!%center%''Inflexion Research Project Under Usine Logicielle Project(Research fellow at the CEA/Sacaly)''

%center%http://www.usine-logicielle.org
\\


The
work is conducted in the context of a national French project called Usine Logicielle. This project is three-folded : modeling, validation and infrastructure/middleware support along with configuration support.

\
\\
\\

----
to:
'''Research Interests & Projects'''%0a----%0a\\%0a%0a%25lframe width=150px height=55px%25 [[ http://www.teresa-project.org/ | Attach:logoTERESA.jpg]]%25%25%0a!!!!!%25center%25''TERESA:Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7''%0a%25left%25 http://www.teresa-project.org/%0a%0a%0aThe work is conducted in the context of Small or medium-scale focused research project (STREP) proposal ICT Call 4 FP7-ICT-2009-4%0a%0a%0aThe objective of TERESA is to define, demonstrate and validate an engineering discipline for trust that is adapted to resource constrained embedded systems. We define trust as the degree with which security and dependability requirements are met.%0a%0aPartners are:%0a* IRIT Toulouse (France) : modelling, dependability%0a* Fraunhofer (Germany): Formal validation of security and dependability%0a* Trialog (France): tools, trust models elicitation, home control, automotive applications%0a* Ikerlan-K4 (Spain): industry control applications%0a* Escrypt (Germany): security for embedded systems%0a* U.Siegen (Germany): security for metrology%0a%0a%0a%0a----%0a%25lframe width=150px height=55px%25 Attach:logoSIRSEC.jpg%0a!!!!!%25center%25''SIRSEC: SystÚme d'Information Reparti Sécuritaire(2009-2013) -- FUI7''%0a%0a\\%0aThe work is conducted in the context of a national French project. %0a%0aPartners are:%0a%0a*IRIT, CEA LIST and INRETS LEOST (Academics): to help the improvement of the development of distributed secure systems using model based engineering %0a* ALSTOM TRANSPORT and Thales (Industrials): to reduce the cost of the life cycle of development process of novel architecture with support of extended services%0a* PRISMTECH, SERMA Ing. and GEENSYS (Software editors): to extend their offers of middleware and tools with support of safety and validation %0a----%0a!!!!!%25center%25''Inflexion Research Project Under Usine Logicielle Project(Research fellow at the CEA/Sacaly)''%0a%0a%25center%25http://www.usine-logicielle.org%0a\\%0a%0a%0aThe work is conducted in the context of a national French project called Usine Logicielle. This project is three-folded : modeling, validation and infrastructure/middleware support along with configuration support.
March 19, 2018, at 08:40 PM by 141.115.28.6 -
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!!!!!%center%''SIRSEC: Système d'Information Reparti Sécuritaire(2009-2013) -- FUI7''
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!!!!!%center%''SIRSEC: d'Information Reparti (2009-2013) -- FUI7''
March 26, 2017, at 06:08 PM by 141.115.28.6 -
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March 26, 2017, at 06:08 PM by 141.115.28.6 -
March 26, 2017, at 06:08 PM by 141.115.28.6 -
March 08, 2016, at 05:05 PM by 141.115.28.6 -
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The work is conducted in the context of a national French project called �Usine Logicielle� . This project is three-folded : modeling, validation and infrastructure/middleware support along with configuration support.
to:
The work is conducted in the context of a national French project called Usine Logicielle. This project is three-folded : modeling, validation and infrastructure/middleware support along with configuration support.
March 08, 2016, at 05:04 PM by 141.115.28.6 -
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!!!!!%center%''SIRSEC: Reparti (2009-2013) -- FUI7''
to:
!!!!!%center%''SIRSEC: Système d'Information Reparti Sécuritaire(2009-2013) -- FUI7''
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The work is conducted in the context of a national French project called . This project is three-folded : modeling, validation and infrastructure/middleware support along with configuration support.
to:
The work is conducted in the context of a national French project called �Usine Logicielle� . This project is three-folded : modeling, validation and infrastructure/middleware support along with configuration support.
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!!!!!%center%''TERESA:Trusted computing Engineering for Resource constrained Embedded Systems Applications (on going) -- FP7''
to:
!!!!!%center%''TERESA:Trusted computing Engineering for Resource constrained Embedded Systems Applications (2009-2013) -- FP7''
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!!!!!%center%''SIRSEC: Reparti (on going) -- FUI7''
to:
!!!!!%center%''SIRSEC: Reparti (2009-2013) -- FUI7''