Advance program

Room
Sept. 30, Sunday  
14:00-17:00 Tutorial: Compiling Code Accelerators for FPGAs, Walid Najjar, UC Riverside, USA Paracelsus
Oct. 1, Monday  
08:30-09:00 Esweek opening
09:00-10:00 EMSOFT Keynote: User-Centered Approach for Semi-Automatic, Assistive Devices and Systems
Jane Liu, Academia Sinica, TAIWAN
Mozartsaal
10:00-10:30 Coffee Break
10:30-12:00 Session 1 - Embedded Development Tools Paracelsus
A Fast and Generic Hybrid Simulation Approach Using C Virtual Machine
Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. RWTH Aachen University, GERMANY
Compiler Generation from Structural Architecture Descriptions.
Florian Brandner, Dietmar Ebner, and Andreas Krall. Vienna University of Technology, AUSTRIA
Non-Transparent Debugging For Software-Pipelined Loops
Hugo Venturini, Frederic Riss, Jean-Claude Fernandez, Miguel Santana. STMicroelectronics, FRANCE
12:00:13:30 Lunch
13:30-15:30 Session 2 - Short Presentations with Posters Paracelsus
An Integrated ARM and multi-core DSP simulator
Sharad Singhai, Mingyung Ko, Mayan Moudgill, Sanjay Jinturkar, John Glossner. Sandbridge Technologies, USA
SCCP/x - A Compilation Profile to Support Testing and Verification of Optimized Code
Raimund Kirner. Vienna University of Technology, AUSTRIA
Performance-Driven Syntax-Directed Synthesis of Asynchronous Embedded Processors
Luis A. Plana, Doug Edwards and Sam Taylor. University of Manchester, UNITED KINGDOM
Stack Size Reduction of Programs
Stefan Schaeckeler, Weijia Shang. Santa Clara University, USA
Performance Evaluation and Optimization of Dual-Port SDRAM Architecture for Mobile Embedded Systems
Hoeseok Yang, Sungchan Kim, Hae-woo Park, Jinwoo Kim, Soonhoi Ha. Seoul National University, SOUTH KOREA
A Hybrid Code Compression Technique using Bitmask and Prefix Encoding with Enhanced Dictionary Selection
Syed I. Haider and Leyla Nazhandali. Virginia Tech, USA
15:30-16:00 Coffee Break
16:00-18:00 Session 3 - Scratchpad Memories Paracelsus
INVITED TALK: “Techniques for Code and Data management in the Local Stores of the Cell Processor”
Kevin O'Brien, IBM Thomas J. Watson, USA
Recursive Function Allocation to Scratch-Pad Memory for Embedded Systems
Angel Dominguez, Nghi Nguyen and Rajeev Barua. University of Maryland, USA
Fragment Cache Management for Dynamic Binary Translators in Embedded Systems with Scratchpad Memory
Jose Baiocchi, Bruce R. Childers, Jack W. Davidson, Jason Hiser, and Jonathan Misurda. University of Pittsburgh, USA
Scratch-Pad Memory Allocation without Compiler Supports for Interpreted-Language based Applications
Nghi Nguyen and Rajeev Barua. University of Maryland, USA
18:00-19:00 EMSOFT Panel: Grand Challenges in Embedded Software
Oct. 2, Tuesday
09:00-10:00 CODES+ISSS Keynote: Complexity Challenges towards 4th Generation Communication Solutions
Hermann Eul, Infineon, GERMANY
Mozartsaal
10:00-10:30 Coffee Break
10:30-12:00 Session 4A - Applications Karajan
Towards Understanding Architectural Tradeoffs in MEMS Closed-Loop Feedback Control
Greg Hoover, Tim Sherwood, Forrest Brewer. University of California, USA
Application Driven Embedded System Design: A Face Recognition Case Study
Karthik Ramani, Al Davis. University of Utah, USA
Hierarchical Coarse-grained Stream Compilation for Software Defined Radio
Yuan Lin, Manjunath Kudlur, Scott Mahlke, Trevor Mudge. University of Michigan, USA
10:30-11:30 Session 4B - Instruction-Set Extension Paracelsus
Rethinking Custom ISE Identification: A New Processor-Agnostic Method
Ajay K. Verma, Philip Brisk, Paolo Ienne. Ecole Polytechnique Federale de Lausanne, SWITZERLAND
An Efficient Framework for Dynamic Reconfiguration of Instruction-Set Customization
Huynh Phung Huynh, Joon Edward Sim, Tulika Mitra. National University of Singapore, SINGAPORE
12:00:13:30 Lunch
13:30-15:30 Session 5 - Short Presentations with Posters Paracelsus
Lightweight Barrier-based Parallelization support for Non-cache-coherent MPSoC Platforms
Andrea Marongiu, Luca Benini, Mahmut Kandemir. University of Bologna, ITALY
Light-weight Synchronization for Interprocessor Communication Acceleration on Embedded MPSoCs
Chengmo Yang and Alex Orailoglu. UCSD, USA
Supporting Multithreading in Configurable Soft Processor Cores
Roger Moussali, Nabil Ghanem, and Mazen A. R. Saghir. American University of Beirut, LEBANON
A Group-Based Wear-Leveling Algorithm for Large-Capacity Flash Memory Storage Systems
Dawoon Jung, Yoon-Hee Chae, Heeseung Jo, Jin-Soo Kim, and Joonwon Lee. KAIST, REPUBLIC OF KOREA
Facilitating Compiler Optimizations through the Dynamic Mapping of Alternate Register Structures
Christopher Zimmer, Steve Hines, Prasaad Kulkarni, Gary Tyson, David Whalley. Florida State University, USA
15:30-16:00 Coffee Break
16:00-18:00 Session 6 - Memory Systems Paracelsus
Vertical Object Layout and Compression for Fixed Heaps
Ben L. Titzer and Jens Palsberg. UCLA, USA
Software Controlled Memory Layout Reorganization for Irregular Array Access Patterns
Doosan Cho, Ilya Issenin, Nikil Dutt, Yunheung Paek. Seoul National University, KOREA
A Self-maintained Memory Module Supporting Explicit Memory Management
Weixing JI, Feng SHI, Baojun QIAO. Beijing Institute of Technology, CHINA
Eliminating Inter-Process Cache Interference through Cache Reconfigurability for Real-Time and Low-Power Embedded Multi-Tasking Systems
Rakesh Reddy and Peter Petrov. University of Maryland, USA
18:00-19:00 ACM SIGBED Business Meeting 
19:30-22:00 Banquet
Oct. 3, Wednesday  
09:00-10:00 CASES Keynote: Multicore Architectures, Trevor Mudge, The University of Michigan, Ann Arbor Mozartsaal
10:00-10:30 Coffee Break
10:30-12:00 Session 7 - Compilation / Code Generation Paracelsus
An Optimistic and Conservative Register Assignment Heuristic for Chordal Graphs
Philip Brisk, Ajay K. Verma, and Paolo Ienne. Ecole Polytechnique Federale de Lausanne, SWITZERLAND
A Simplified Java Compilation System for Resource-Constrained Embedded Processors
Carmen Badea, Alexandru Nicolau, Alex Veidenbaum. UC Irvine, USA
A Backtracking Instruction Scheduler using Predicate-based Code Hoisting to Fill Delay Slots
Tom Vander Aa, Bing-Feng Mei, Bjorn De Sutter. IMEC, BELGIUM
12:00:13:30 Lunch
13:30-15:30 Session 8 - Low Power and Thermal-Aware Architectures Paracelsus
INTACTE: An Interconnect Area, Delay, and Energy Estimation Tool for Microarchitectural Explorations
Rahul Nagpal, Arvind Madan, Amrutur Bharadwaj, and Y. N. Srikant. Indian Institute of Science, Computer Science and Automation, INDIA
Cache Leakage Control Mechanism for Hard Real-Time Systems
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen. National Taiwan University, TAIWAN
Performance optimal throttling of processors under thermal constraints
Ravishankar Rao and Sarma Vrudhula. Arizona State University, USA
A Low Power Front-End for Embedded Processors Using a Block-Aware Instruction Set
Ahmad Zmily, Christos Kozyrakis. Standford University, USA
15:30-16:00 Coffee Break
16:00-17:30 CODES+ISSS Panel 
17:30-18:00 ESWEEK Main Conferences Closing Remarks

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