Publications of
Roman Bourgade, Christine Rochange, Pascal Sainrat
Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets (regular paper)
In : International Conference on Architecture of Computing Systems (ARCS 2012), Prague, 19/02/12-23/02/13, Springer, pp. 341-351, February 2013.
Roman Bourgade, Christine Rochange, Pascal Sainrat
Predictable Bus Arbitration Schemes for Heterogeneous Time-Critical Workloads Running on Multicore Processors (short paper)
In : Emerging Technologies and Factory Automation (ETFA 2011), Toulouse, 05/09/11-09/09/11, IEEE : Institute of Electrical and Electronics Engineers, pp. 1-4, September 2011.
Abstract URL : http://www.irit.fr/publis/TRACES/12619_etfa2011.pdf
BibTeXRoman Bourgade, Christine Rochange, Marianne De Michiel, Pascal Sainrat
MBBA: a Multi-Bandwidth Bus Arbiter for hard real-time (regular paper)
In : International Conference on Embedded and Multimedia Computing (EMC 2010), Cebu, Philippines, 11/08/10-13/08/10, IEEE : Institute of Electrical and Electronics Engineers, pp. 1-8, August 2010 (Best paper).
URL : http://www.irit.fr/publis/TRACES/11588_emc2010-bourgade-final.pdf
BibTeXNiklas Holsti, Jan Gustafsson, Guillem Bernat, Clément Ballabriga, Armelle Bonenfant, Roman Bourgade, Hugues Cassé, Daniel Cordes, Albrecht Kadlec, Raimund Kirner, Jens Knoop, Paul Lokuciejewski, Nicholas Merriam, Marianne De Michiel, Adrian Prantl, Bernhard Rieder, Christine Rochange, Pascal Sainrat, Markus Schordan
WCET Tool Challenge 2008: report
In : International Workshop on Worst-Case Execution Time Analysis (WCET 2008), Prague, 01/07/08-01/07/08, Austrian Computer society, pp. 149-171, October 2008.
URL : http://www.irit.fr/publis/TRACES/9687_challenge08.pdf
BibTeXRoman Bourgade, Clément Ballabriga, Hugues Cassé, Christine Rochange, Pascal Sainrat
Accurate analysis of memory latencies for WCET estimation (regular paper)
In : International Conference on Real-Time and Network Systems (RTNS 2008), Rennes, 16/10/08-17/10/08, IRISA, pp. 161-170, October 2008.
URL : http://www.irit.fr/publis/TRACES/9445_rtns08final.pdf
BibTeX
Analyse du temps d’exécution pire-cas de tâches temps-réel exécutées sur une architecture multi-curs
Master’s Thesis, Université de Toulouse, October 2012.
URL : http://www.irit.fr/publis/TRACES/these_roman_bourgade_22102012.pdf
BibTeX