Jean-Luc Gaudiot, Université de Californie à Irvine
Value Prediction in Parallel Architectures

The newly emerging many-core-on-a-chip designs have renewed an intense interest in parallel processing. By applying Amdahl’s formulation to the programs in the PARSEC and SPLASH-2 benchmark suites, we find that most applications may not have sufficient parallelism to efficiently utilize modern parallel machines. The long sequential portions in these application programs are caused by computation as well as communication latency. However, value prediction techniques may allow the “parallelization” of the sequential portion by predicting values before they are produced. In conventional superscalar architectures, the computation latency dominates the sequential sections. Thus value prediction techniques may be used to predict the computation result before it is produced. In many-core architectures, since the communication latency increases with the number of cores, value prediction techniques may be used to reduce both the communication and computation latency. We extend these ideas by using GPUs to accelerate programs that contain limited parallelism and those that are hard to parallelize.


Jean-Luc Gaudiot is currently a Professor in the Electrical Engineering and Computer Science Department at the University of California, Irvine. In January 2006, he became the first Editor-in-Chief of the IEEE Computer Architecture Letters, a new publication of the IEEE Computer Society, which he helped found to the end of facilitating short, fast turnaround of fundamental ideas in the Computer Architecture domain. His research interests include multithreaded architectures, fault-tolerant multiprocessors, and implementation of reconfigurable architectures.