CAPITAL Workshop 2023: sCalable And PrecIse Timing AnaLysis for multicore platforms

Date: June 13th, 2023

Place: IRIT, Université Paul Sabatier, Toulouse, France (google maps)

Zoom link: https://univ-tlse3-fr.zoom.us/j/98177573330

Registration is free but mandatory to help us prepare the venue (register link)

Keynote

Prof. Jian-Jia Chen, Department of Informatics, TU Dortmund University, Germany:

Property-Based Timing Analysis and Optimization for Complex Cyber-Physical Real-Time Systems (PDF)

Cyber-physical real-time systems are information processing systems that require both functional as well as timing correctness and have interactions with the physical world. Since time naturally progresses in the physical world, safe bounds of deterministic or probabilistic timing properties are required. It is essential to construct timing analysis for complex cyber-physical real-time systems from formal properties. In this talk, I will utilize a few examples to demonstrate the needs of such property-based modular timing analysis. Furthermore, I will illustrate how to utilize proper properties to achieve safe analysis for real-time communication, deadline miss (failure) probability, and multiprocessor gang scheduling. At the end of the talk, I will shortly discuss the outlook of such property-based timing analysis based on the ERC Consolidator project PropRT.

Bio: Jian-Jia Chen is Professor at the Department of Informatics in TU Dortmund University in Germany. He was Junior professor at the Department of Informatics in Karlsruhe Institute of Technology (KIT) in Germany from May 2010 to March 2014. He received his Ph.D. degree from the Department of Computer Science and Information Engineering, National Taiwan University, Taiwan in 2006. He received his B.S. degree from the Department of Chemistry at National Taiwan University 2001. Between Jan. 2008 and April 2010, he was a postdoc researcher at ETH Zurich, Switzerland. His research interests include real-time systems, embedded systems, energy-efficient scheduling, power-aware designs, temperature-aware scheduling, and distributed computing. He received the European Research Council (ERC) Consolidator Award in 2019. He has received more than 10 Best Paper Awards and Outstanding Paper Awards and has involved in Technical Committees in many international conferences.

Invited speakers

Benjamin Binder, CEA, Paris-Saclay, France: Formal Definitions and Detection Procedures of Timing Anomalies for the Predictability of Real-Time Systems (PDF)

Björn Forsberg, RISE Research Institutes of Sweden, Computer Systems group, Sweden: Multi-Target Compiler for the PREM Three Phase Execution Model for COTS Real-Time Systems (PDF | link to compiler)

Alfonso Mascarenas Gonzales, ONERA, Toulouse, France: Memory Interference Analysis on Heterogeneous MPSoCs (PDF | PPT)

Syed Aftab Rashid, CISTER/ISEP and VORTEX Colab, Porto, Portugal: Cache-aware Schedulability Analysis of PREM Compliant Tasks (PDF)

Matteo Zini, University Sant’Anna, Pisa, Italy: Analyzing Arm’s MPAM From the Perspective of Time Predictability (PDF | PPT)

Program

9:00am: Keynote from Jian-Jia Chen

10:00am: Coffee break

10:15am: Matteo Zini: Analyzing Arm’s MPAM From the Perspective of Time Predictability

11:05am: Benjamin Binder: Formal Definitions and Detection Procedures of Timing Anomalies for the Predictability of Real-Time Systems

12:00: lunch break

1:30pm: Björn Forsberg: Multi-Target Compiler for the PREM Three Phase Execution Model for COTS Real-Time Systems

2:20pm: Syed Aftab Rashid: Cache-aware Schedulability Analysis of PREM Compliant Tasks

3:10pm: Coffee break

3:25pm: Alfonso Mascarenas Gonzales: Memory Interference Analysis on Heterogeneous MPSoCs

4:15pm: End of the workshop

General topic of the workshop

The design and the implementation of time-critical applications upon multi-core processors are considered. Multi-core processors have the potential to offer high computing power. Unfortunately, their extensive use of shared resources (e.g. caches, DRAM, buses, etc.) makes the design and the implementation difficult to predict — especially in situations where hard real-time constraints must be satisfied. Recent works show that an important challenge is to design a precise and scalable timing analysis. To address this challenge the research community considers closely both sides of the system: software and hardware. The aim of this co-design approach is therefore to guarantee scalability, precision and low complexity of the solution without compromising flexible efficient use of resources. The solution must be tailored for the target application and platform. In particular by identifying the shared resources (memory, bus, cache) and by reducing the complexity based on interference delay using, for instance, a tailored mapping/scheduling, bandwidth regulator. The solution must be also based on a good use of the hardware architecture (memory banks, cache, communication media) with techniques like physical/temporal partitioning to obtain a precise solution.

Organisers

Thomas Carle (Université Toulouse III Paul Sabatier, IRIT, France)

Steering Commitee

Joël Goossens (ULB, Brussels, Belgium)
Claire Maiza (Grenoble INP/Ensimag, Verimag, Grenoble, France)
Juan M Rivas (Universidad de Cantabria, Santander, Spain)