Research Interests & Projects
TERESA:Trusted computing Engineering for Resource constrained Embedded Systems Applications (on going) -- FP7
The work is conducted in the context of Small or medium-scale focused research project (STREP) proposal ICT Call 4 FP7-ICT-2009-4
The objective of TERESA is to define, demonstrate and validate an engineering discipline for trust that is adapted to resource constrained embedded systems. We define trust as the degree with which security and dependability requirements are met.
- IRIT Toulouse (France) : modelling, dependability
- Fraunhofer (Germany): Formal validation of security and dependability
- Trialog (France): tools, trust models elicitation, home control, automotive applications
- Ikerlan-K4 (Spain): industry control applications
- Escrypt (Germany): security for embedded systems
- U.Siegen (Germany): security for metrology
SIRSEC: Système d’Information Reparti Sécuritaire(on going) -- FUI7
The work is conducted in the context of a national French project.
- IRIT, CEA LIST and INRETS LEOST (Academics): to help the improvement of the development of distributed secure systems using model based engineering
- ALSTOM TRANSPORT and Thales (Industrials): to reduce the cost of the life cycle of development process of novel architecture with support of extended services
- PRISMTECH, SERMA Ing. and GEENSYS (Software editors): to extend their offers of middleware and tools with support of safety and validation
Inflexion Research Project Under Usine Logicielle Project(Research fellow at the CEA/Sacaly)
The work is conducted in the context of a national French project called “Usine Logicielle” . This project is three-folded : modeling, validation and infrastructure/middleware support along with configuration support.