TORRENTS

Seminar by Fabian Vargas (PUCRS, Brazil): Design of On-Chip Cores and Sensors to Improve Embedded System Reliability

This talk discusses recent research that has been carried out at the Catholic University - PUCRS dealing to enhance the reliability of System-on-Chip (SoC) devoted to critical embedded real-time applications. The goal of this talk is twofold:
(a) It describes the development of an intellectual property (IP) core to monitor embedded software activity. In this sense, an IP core has been developed to check two types of software activities: first, the IP core monitors the “task scheduling process” carried out by the operating system (OS) kernel. Second, the IP core monitors the “worst-case execution time (WCET)” of embedded applications running under the OS control. In both cases, the monitoring deals with on-line detection of control-flow and/or timing errors, on the field.
(b) Secondly, this talk addresses the development of on-chip sensors to monitor three issues: first, on-chip sensor is used to\ detect dynamic resistive open defects in nano-SRAMs; second, a dedicated sensor is used to monitor aging effects that reduce very-deep submicron (VDSM) SRAMs lifetime. A modified version of this sensor has been developed to monitor aging of logic implemente\d in field programmable gate arrays (FPGAs). Third, on-chip sensor is used to detect single-event upsets (SEUs) in SRAMs exposed \to radiation. In this case, on-chip sensor is coupled with parity code to allow error detection and correction of radiation-induced soft errors in SRAM cells.
slides (part 1)   slides (part 2)