Traces is a Research group on Architectures and Compilers for Embedded Systems

Research

Simulation

Simulation is a key technique for performance evaluation. It is also involved in WCET evaluation to measure the execution times of small parts of code.

Instruction set simulation

The simulator of a processor architecture includes a functional part, that simulates the instruction set, and a timing part, that simulates the architecture at the cycle-level. We have developed the GLISS tool that generates a functional simulator from a textual description of the instruction set.

Participants: Tahiry Ratsiambahotra, Pascal Sainrat