Traces is a Research group on Architectures and Compilers for Embedded Systems
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People
Faculty
Armelle Bonenfant
Cassé
De Michiel
Kebbal
Rochange
Sainrat
Post-doctoral researchers
Ozaktas
PhD students
Bourgade
Herbegue
Former members
Burguière
Duloum
Haquin
Landet
Nemer
Nicolas Curt
Ratsiambahotra
Reynes
Soulier
Tawk
Research
Evaluation of Worst-Case Execution Times
Incremental WCET evaluation
Models for advanced architectures
Predictable timing behaviour: architecture and compilation
Predictable instruction scheduling
Static branch prediction
Simulation
Instruction set simulation
Papers
2005
A Case for Static Branch Prediction in Real-Time Systems
A contribution to branch prediction modeling in WCET analysis
A Time-Predictable Execution Mode for Superscalar Pipelines with Instruction Prescheduling
Analysing branch mispredictions related to algorithmic constructs
CBSP: a Predictor of Sequences of Correlated Branches
Dissecting Execution Traces to Understand Long Timing Effects
Modélisation d’un prédicteur de branchement bimodal dans le calcul du WCET par la méthode IPET
Régulation du flot d’instructions pour des processeurs orientés temps-réel
2006
Automatic Flow Analysis using Symbolic Execution and Path Enumeration
Code padding to improve the WCET calculability
Combining Symbolic Execution and Path Enumeration in Worst-Case Execution Time Analysis
History-based Schemes and Implicit Path Enumeration
Modeling Instruction-Level Parallelism for WCET Evaluation
OTAWA, a framework for experimenting WCET computations
PapaBench : A Free Real-Time Benchmark
2007
A Context-Parameterized Model for Static Analysis of Execution Times
Automatic Amortised Worst-Case Execution Time Analysis
High-Performance Embedded Architecture and Compilation Roadmap
Improving the WCET accuracy by inter-task instruction cache analysis
On the Complexity of Modelling Dynamic Branch Predictors when Computing Worst-Case Execution Times
On the sensitivity of WCET estimates to the variability of basic blocks execution times
OTAWA, Open Tool for Adaptative WCET Analysis
WCET computation on software components by partial static analysis
2008
A Predictable Simultaneous Multithreading Scheme for Hard Real-Time
Accurate analysis of memory latencies for WCET estimation
An Architecture for the Simultaneous Execution of Hard Real-Time Threads
An Improved Approach for Set-associative Instruction Cache Partial Analysis
Improving the First-Miss Computation in Set-Associative Instruction Caches
Improving the WCET computation time by IPET using control flow graph partitioning
Inter-Task WCET computation for A-way Instruction Caches
Static loop bound analysis of C programs based on flow analysis and abstract interpretation
2009
A Generic Framework for Blackbox Components in WCET Computation
A Versatile Generator of Instruction Set Simulators and Disassemblers
Impact of Code Compression on Estimated Worst-Case Execution Times
2010
A Design Flow for Critical Embedded Systems
A framework to experiment optimizations for real-time and embedded software
An automatic parametric approach for WCET analysis of C programs
Experimentation of WCET computation on both ends of automotive processor range
MBBA: a Multi-Bandwidth Bus Arbiter for hard real-time
OTAWA: an Open Toolbox for Adaptive WCET Analysis
Partial Flow Analysis with oRange
RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-Core Processor
WCET Analysis of a Parallel 3G Multigrid Solver Executed on the MERASA Multi-core
2011
A framework for the timing analysis of dynamic branch predictors
An overview of approaches towards the timing analysability of parallel architectures
Fast Instruction-Accurate Simulation with SimNML
Predictable Bus Arbitration Schemes for Heterogeneous Time-Critical Workloads Running on Multicore Processors
Validation of real-time properties of a robotic software architecture
Projects
Analyse et optimisation des processeurs et applications embarqués/spécialisés
ATLAS
COP
Investigation of real-time capable embedded SMT processor techniques
MasCotTE
MERASA
MORE
Multithreaded Processor Design
parMERASA
PATER
SOCKET
Tools
frontC
Description
Download
GLISS
Description
Downloads
OTAWA
Description
PapaBench
Description
FAQ
Links
Calls for papers
11th Int’l Conference on Embedded Software
11th Int’l workshop on Worst-Case Execution Time (WCET) Analysis
14th International Workshop on Software and Compilers for Embedded Systems
16th IEEE International Conference on Emerging Technologies and Factory Automation
18th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
18th IEEE Real-Time and Embedded Technology and Applications Symposium
19th International Conference on Real-Time Networks and Systems
24th Euromicro Conference on Real-Time Systems
27th ACM Symposium on Applied Computing, track on Embedded Systems
32nd IEEE Real-Time Systems Symposium
39th Annual International Symposium on Computer Architecture
6th ACM/IEEE International Symposium on Code Generation and Opti
9th Int’l Conf. on Formal Modeling and Analysis of Timed Systems
ACM Conference on Languages, Compilers, and Tools for Embedded Systems
ACM Int. Conf. on Computing Frontiers
Design, Automation and Test in Europe
Embedded Real Time Software and Systems
IEEE 7th Symposium on Industrial Embedded Systems
Int’l Conference on Compilers, Architecture and Synthesis for Embedded Systems
Int’l Conference on Hardware-Software Codesign and System Synthesis
International Conference on Architecture of Computing Systems
International Symposium on Systems, Architectures, MOdeling and Simulation
SYMPosium en Architectures nouvelles de machines
Groups
HiPEAC: European Network of Excellence on High-Performance and Embedded Architectures and Compilers
WWW Computer Architecture Page
Miscellanea
embedded.com
Intel Technology Journal
On-line publications
Computer Architecture Letters
IEEE Xplore
Journal of Instruction-Level Parallelism
Real-Time Systems (Kluwer)