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Room |
| Sept. 30, Sunday |
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| 14:00-17:00 |
Tutorial: Compiling Code Accelerators for FPGAs, Walid Najjar, UC Riverside, USA |
Paracelsus |
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| Oct. 1, Monday |
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| 08:30-09:00 |
Esweek opening |
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| 09:00-10:00 |
EMSOFT Keynote: User-Centered Approach for Semi-Automatic, Assistive Devices and Systems
Jane Liu, Academia Sinica, TAIWAN |
Mozartsaal |
| 10:00-10:30 |
Coffee Break |
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| 10:30-12:00 |
Session 1 - Embedded Development Tools |
Paracelsus |
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A Fast and Generic Hybrid Simulation Approach Using C Virtual Machine
Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. RWTH Aachen University, GERMANY |
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Compiler Generation from Structural Architecture Descriptions.
Florian Brandner, Dietmar Ebner, and Andreas Krall. Vienna University of Technology, AUSTRIA |
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Non-Transparent Debugging For Software-Pipelined Loops
Hugo Venturini, Frederic Riss, Jean-Claude Fernandez, Miguel Santana. STMicroelectronics, FRANCE |
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| 12:00:13:30 |
Lunch |
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| 13:30-15:30 |
Session 2 - Short Presentations with Posters |
Paracelsus |
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An Integrated ARM and multi-core DSP simulator
Sharad Singhai, Mingyung Ko, Mayan Moudgill, Sanjay Jinturkar, John Glossner. Sandbridge Technologies, USA |
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SCCP/x - A Compilation Profile to Support Testing and Verification of Optimized Code
Raimund Kirner. Vienna University of Technology, AUSTRIA |
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Performance-Driven Syntax-Directed Synthesis of Asynchronous Embedded Processors
Luis A. Plana, Doug Edwards and Sam Taylor. University of Manchester, UNITED KINGDOM |
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Stack Size Reduction of Programs
Stefan Schaeckeler, Weijia Shang. Santa Clara University, USA |
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Performance Evaluation and Optimization of Dual-Port SDRAM Architecture for Mobile Embedded Systems
Hoeseok Yang, Sungchan Kim, Hae-woo Park, Jinwoo Kim, Soonhoi Ha. Seoul National University, SOUTH KOREA |
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A Hybrid Code Compression Technique using Bitmask and Prefix Encoding with Enhanced Dictionary Selection
Syed I. Haider and Leyla Nazhandali. Virginia Tech, USA |
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| 15:30-16:00 |
Coffee Break |
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| 16:00-18:00 |
Session 3 - Scratchpad Memories |
Paracelsus |
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INVITED TALK: “Techniques for Code and Data management in the Local Stores of the Cell Processor”
Kevin O'Brien, IBM Thomas J. Watson, USA |
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Recursive Function Allocation to Scratch-Pad Memory for Embedded Systems
Angel Dominguez, Nghi Nguyen and Rajeev Barua. University of Maryland, USA |
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Fragment Cache Management for Dynamic Binary Translators in Embedded Systems with Scratchpad Memory
Jose Baiocchi, Bruce R. Childers, Jack W. Davidson, Jason Hiser, and Jonathan Misurda. University of Pittsburgh, USA |
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Scratch-Pad Memory Allocation without Compiler Supports for Interpreted-Language based Applications
Nghi Nguyen and Rajeev Barua. University of Maryland, USA |
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| 18:00-19:00 |
EMSOFT Panel: Grand Challenges in Embedded Software |
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| Oct. 2, Tuesday |
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| 09:00-10:00 |
CODES+ISSS Keynote: Complexity Challenges towards 4th Generation Communication Solutions
Hermann Eul, Infineon, GERMANY |
Mozartsaal |
| 10:00-10:30 |
Coffee Break |
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| 10:30-12:00 |
Session 4A - Applications |
Karajan |
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Towards Understanding Architectural Tradeoffs in MEMS Closed-Loop Feedback Control
Greg Hoover, Tim Sherwood, Forrest Brewer. University of California, USA |
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Application Driven Embedded System Design: A Face Recognition Case Study
Karthik Ramani, Al Davis. University of Utah, USA |
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Hierarchical Coarse-grained Stream Compilation for Software Defined Radio
Yuan Lin, Manjunath Kudlur, Scott Mahlke, Trevor Mudge. University of Michigan, USA |
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| 10:30-11:30 |
Session 4B - Instruction-Set Extension |
Paracelsus |
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Rethinking Custom ISE Identification: A New Processor-Agnostic Method
Ajay K. Verma, Philip Brisk, Paolo Ienne. Ecole Polytechnique Federale de Lausanne, SWITZERLAND |
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An Efficient Framework for Dynamic Reconfiguration of Instruction-Set Customization
Huynh Phung Huynh, Joon Edward Sim, Tulika Mitra. National University of Singapore, SINGAPORE |
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| 12:00:13:30 |
Lunch |
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| 13:30-15:30 |
Session 5 - Short Presentations with Posters |
Paracelsus |
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Lightweight Barrier-based Parallelization support for Non-cache-coherent MPSoC Platforms
Andrea Marongiu, Luca Benini, Mahmut Kandemir. University of Bologna, ITALY |
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Light-weight Synchronization for Interprocessor Communication Acceleration on Embedded MPSoCs
Chengmo Yang and Alex Orailoglu. UCSD, USA |
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Supporting Multithreading in Configurable Soft Processor Cores
Roger Moussali, Nabil Ghanem, and Mazen A. R. Saghir. American University of Beirut, LEBANON |
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A Group-Based Wear-Leveling Algorithm for Large-Capacity Flash Memory Storage Systems
Dawoon Jung, Yoon-Hee Chae, Heeseung Jo, Jin-Soo Kim, and Joonwon Lee. KAIST, REPUBLIC OF KOREA |
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Facilitating Compiler Optimizations through the Dynamic Mapping of Alternate Register Structures
Christopher Zimmer, Steve Hines, Prasaad Kulkarni, Gary Tyson, David Whalley. Florida State University, USA |
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| 15:30-16:00 |
Coffee Break |
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| 16:00-18:00 |
Session 6 - Memory Systems |
Paracelsus |
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Vertical Object Layout and Compression for Fixed Heaps
Ben L. Titzer and Jens Palsberg. UCLA, USA |
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Software Controlled Memory Layout Reorganization for Irregular Array Access Patterns
Doosan Cho, Ilya Issenin, Nikil Dutt, Yunheung Paek. Seoul National University, KOREA |
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A Self-maintained Memory Module Supporting Explicit Memory Management
Weixing JI, Feng SHI, Baojun QIAO. Beijing Institute of Technology, CHINA |
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Eliminating Inter-Process Cache Interference through Cache Reconfigurability for Real-Time and Low-Power Embedded Multi-Tasking Systems
Rakesh Reddy and Peter Petrov. University of Maryland, USA |
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| 18:00-19:00 |
ACM SIGBED Business Meeting |
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| 19:30-22:00 |
Banquet |
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| Oct. 3, Wednesday |
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| 09:00-10:00 |
CASES Keynote: Multicore Architectures, Trevor Mudge, The University of Michigan, Ann Arbor |
Mozartsaal |
| 10:00-10:30 |
Coffee Break |
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| 10:30-12:00 |
Session 7 - Compilation / Code Generation |
Paracelsus |
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An Optimistic and Conservative Register Assignment Heuristic for Chordal Graphs
Philip Brisk, Ajay K. Verma, and Paolo Ienne. Ecole Polytechnique Federale de Lausanne, SWITZERLAND |
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A Simplified Java Compilation System for Resource-Constrained Embedded Processors
Carmen Badea, Alexandru Nicolau, Alex Veidenbaum. UC Irvine, USA |
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A Backtracking Instruction Scheduler using Predicate-based Code Hoisting to Fill Delay Slots
Tom Vander Aa, Bing-Feng Mei, Bjorn De Sutter. IMEC, BELGIUM |
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| 12:00:13:30 |
Lunch |
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| 13:30-15:30 |
Session 8 - Low Power and Thermal-Aware Architectures |
Paracelsus |
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INTACTE: An Interconnect Area, Delay, and Energy Estimation Tool for Microarchitectural Explorations
Rahul Nagpal, Arvind Madan, Amrutur Bharadwaj, and Y. N. Srikant. Indian Institute of Science, Computer Science and Automation, INDIA |
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Cache Leakage Control Mechanism for Hard Real-Time Systems
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen. National Taiwan University, TAIWAN |
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Performance optimal throttling of processors under thermal constraints
Ravishankar Rao and Sarma Vrudhula. Arizona State University, USA |
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A Low Power Front-End for Embedded Processors Using a Block-Aware Instruction Set
Ahmad Zmily, Christos Kozyrakis. Standford University, USA |
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| 15:30-16:00 |
Coffee Break |
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| 16:00-17:30 |
CODES+ISSS Panel |
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| 17:30-18:00 |
ESWEEK Main Conferences Closing Remarks |
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